FTC Begins Consideration of Industry Input on Rambus Remedies

Updated 9/19/06:  Ah, my good friends the Rambus daytraders have discovered the fact that I have filed another Amicus Brief and (better yet) that I now have a blog where they can leave public comments.  Those who are not members of this community will find their comments below amusing, as they may RMBS and (Another) Dark Side of the Internet, which will help to place them in context

Today is the deadline for filing amicus curiae (friend of the court) briefs and other forms of input with the Federal Trade Commission, as it considers what the punishment of Rambus, Inc. should be for having engaged in "an anticompetitive 'hold up' of the computer memory industry [that]... contributed significantly to Rambus’s acquisition of monopoly power in the four relevant markets."  The FTC made that announcement on August 2, and also announced that it would accept briefs from interested industry participants and others, as well as from Rambus and the FTC prosecuting team.

I've submitted three amicus curiae briefs over the past several years (with the Federal Circuit, Supreme Court, and FTC), on a pro bono basis, in relation to this investigation as well as in connection with the litigation between Rambus and Infineon, on behalf of a large group of standard setting organizations that collectively represent many thousands of corporate, government, university and non-profit members, and was encouraged to provide input in response to this invitation by the FTC as well. 

Below are the "Issue Urged" and "Summary of Argument" from the brief, which will give you an idea of why the Rambus litigation is so important, and why it's equally important that the remedies that the FTC levies send a clear message that, when it comes to abusing the standard setting process, "crime does not pay."  If you'd like to read the whole brief, you can find it in PDF form here.



The remedy levied by the Commission against Rambus must send a clear message to that company, as well as to all that participate in the standard setting process, that the consequences of such bad-faith conduct, if discovered, will significantly exceed the potential gains of engaging in such practices. To fail to include a significant punitive element in the remedies assessed by the Commission would dangerously undermine the standard setting process, to the detriment of society and the national interest.



Standards are vital to government procurement, national competitiveness, and the efficiency and safety of society. Standards are created by voluntary, self-governing organizations that have no effective enforcement power to police the conduct of their members. In the technology sector, the implementation of standards is often likely to result in the infringement of the patents of members and/or non-members. If the owner of a patent that would be infringed by a standard is only willing to license that patent selectively, or on such unreasonable or discriminatory terms as it may wish, then severe consequences will follow, including unreasonable costs to end-users, unfair discrimination against industry participants, and even the complete failure of the standard in question. While the potential for such a result cannot easily be avoided in the case of a patent claim owned by a non-participant in the standard setting process, it is highly inequitable for a participating patent owner to manipulate the process of an SSO in which it was active to ensure such a result for its own benefit.


The value and importance of standards in the modern world is profound. As an example, the Department of Commerce concluded in 2004 that standards affect an estimated 80 percent of world commodity trade. U.S. Department of Commerce, Standards and Competitiveness — Coordinating for Results 1 (May 2004). In the technology sector, the role of standards is particularly crucial, as vital infrastructural elements such as telecommunications, the Internet and the Web literally cannot exist without common agreement on, and implementation of, enabling protocols and other standards.


The suitability of the voluntary, consensus-based standard setting process for creating standards for public, as well as private, interests has been recognized by Congress, which enacted the National Technology Transfer and Advancement Act of 1995 (NTTAA), Pub. L. No. 104-113, 110 Stat. 775 (1996). Under that Act, Congress instructed each Federal agency to utilize standards created by SSOs in preference to “government unique” standards to the extent “practicable.” Other government actions discussed below recognize, and encourage, industry-wide reliance on SSO developed standards. As a result of the promulgation of the NTTAA, the proper functioning of the voluntary consensus-based standard setting system has become vital to the proper functioning of government agencies charged with ensuring national interests as diverse as nuclear power, defense, transportation, healthcare and homeland security.


However, unlike public laws and regulations, standards are developed within a process that is not only entirely self-regulating, but also largely unsupervised, except by those that directly participate. As a result, its success or failure is highly dependent upon trust. If those that participate conclude that abusing the system is too easy to accomplish, and that such abuse is too lightly punished if discovered, then the entire system can find itself in danger of collapse, because the risks of participation and adoption of standards become greater than the benefits to be gained through such participation and adoption. Were such a result to occur, virtually no aspect of society would be immune from the impact of that collapse.


It is not the intention of amici curiae in this brief to advocate for a particular remedy or remedies, with respect to which the Commission will be receiving advice from other knowledgeable sources. Rather, the amici curiae represented by this brief wish to stress the importance of imposing penalties that are sufficiently severe to clearly demonstrate that abusing the voluntary standard setting process cannot prudently be evaluated in terms of simple business risk. To do otherwise would be to send a clear signal not only to Rambus, but to the world at large that there is more to be gained in the United States by “gaming” the standard setting process than by obeying the rules.

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Comments (9)

  1. Did  you read the orginal FTC ruling from there ALJ?Did you read Rambus’s withdrawl letter to JEDCE in 1996?Did you read the CFAC ruling regarding disclosure and the LACK thereof?.Did you read Judge Whyte’s recent ruling regarding the spoilation trial?

    If you did you would not come to this conculsion.Any reasonable person would not!

    • Your  AC brief does make frequent use of the words  ‘participate’ and participant’ with regard to SSB.

      In what ways did Rambus ‘participate’ in the standard setting process?

      Did they  advocate  for the inclusion of their  IP?

      Did they present  anything at any of the SSB meetings?

      What  information did they ‘exploit’ that was not  readily publicly available?

      I think your points would have more relevence if Rambus had taken an
      active role in the  Standard  Setting process [which they did

      One more question; As  Rambus was not allowed to speak or advocate
      their  IP,  by what  coincidence did JEDEC manage to
      a design which exploited Rambus patented technologies? All of the
      infringed IP was rooted in a  RMBS patent well-known to the JEDEC

    • I’m glad to see that the Rambus investors club of Yahoo and
      Investorvillage have arrived, it gives me the opportunity to ask a few
      questions that you might be able to clarify, since you’re so vehement
      in your inquisitions:

      You might as well get it from the start….

      <<What must the bus length be at a data rate of 1 ns? >>

      The bus can be any length as long as all the signal paths are matched, because the clocks are source synchronous.

      But then you knew that already, didn’t you Bilow. Too bad about Appian.>>

      I don’t know any Bilow, but it seems to be some paranoia shared by you RamTards.

      I know what source synchronous clocking is. Does Rambus have any valid
      patents on source synchronous clocking methods, systems or devices to
      accomplish that practice?

      I also know what clocking method is employed in Rambus’ commercial RDRAMS. Does Rambus have any patents on that?

      Here’s what Rambus has patents on:

      <<FIG. 8b illustrates how each device 51, 52 receives each of the
      two bus clock signals at a different time (because of is propagation
      delay along the wires), with constant midpoint in time between the two
      bus clocks along the bus. At each device 51, 52, the rising edge 55 of
      Clock153 is followed by the rising edge 56 of Clock254. Similarly, the
      falling edge 57 of Clock153 is followed by the falling edge 58 of
      Clock254. This waveform relationship is observed at all other devices
      along the bus. Devices which are closer to the clock generator have a
      greater separation between Clock1 and Clock2 relative to devices
      farther from the generator because of the longer time required for each
      clock pulse to traverse the bus and return along line 54, but the
      midpoint in time 59, 60 between corresponding rising or falling edges
      in fixed because, for any given device, the length of each clock line
      between the far end of the bus and that device is equal. Each device
      must sample the two bus clocks and generate its own internal device
      clock at the midpoint of the two.>>

      Ok, so the Rambus devices that are patented generate clocks that are
      aligned in phase with each other along the extent of the bus.

      A source synchronous clocking system would have clocks that vary in
      phase along a bus in a fashion nearly equal to the phase variation of
      the data that are transmitted with the clock.

      Here’s what H&F patented:

      “In the preferred embodiment, two sets of these delay lines are used,
      one to generate the true value of the internal device clock 73, and the
      other to generate the complement 74 without adding any inverter delay.
      The dual circuit allows generation of truly complementary clocks, with
      extremely small skew. The complement internal device clock is used to
      clock the `even` input receivers to sample at time 127, while the true
      internal device clock is used to clock the `odd` input receivers to
      sample at time 125. The true and complement internal device clocks are
      also used to select which data is driven to the output drivers. The
      gate delay between the internal device clock and output circuits
      driving the bus in slightly greater than the corresponding delay for
      the input circuits, which means that the new data always will be driven
      on the bus slightly after the old data has been sampled.”

      So they use the SAME clock to operate both the input samplers and
      output drivers in the system they “invented” in 1990 and that everybody
      and their cat infringes on? Or do you claim otherwise? Did they claim
      otherwise before the USPTO and in Federal District court?


      “One important part of the input/output circuitry generates an internal
      device clock based on early and late bus clocks. Controlling clock skew
      (the difference in clock timing between devices) is important in a
      system running with 2 ns cycles, thus the internal device clock is
      generated so the input sampler and the output driver operate as close
      in time as possible to midway between the two bus clocks.”

      So “clock skew” is the difference in clock timing between devices?
      Hummm. They’re not suggesting that clocks have no skew from device to
      device along their Rambus, are they? But that’s stupid, because the
      data that they’re trying to latch with their “input samplers” does have
      timing skew from device to device”

      A source synchronous clocking scheme would have a timing skew due to
      time of flight from device to device, the accompanying data clock would
      skew equally to the data along such a bus. Rambus teaches against a
      source synchronous clocking method by requiring all modules to derive a
      single clock from the early and late clock signals of its clock loop
      “midway between the two bus clocks” and since “the midpoint in time 59,
      60 between corresponding rising or falling edges in fixed” for each
      module along the bus, the data skew relative to the fixed clocks
      results in portions of the bus where no valid data can be latched.

      “To operate at a 2 ns data rate, the transit time on the bus should
      preferably be kept under 1 ns, to leave 1 ns for the setup and hold
      time of the input receivers (described below) plus clock skew. Thus the
      bus lines must be kept quite short, under about 8 cm for maximum
      performance. Lower performance systems may have much longer lines, e.g.
      a 4 ns bus may have 24 cm lines (3 ns transit time, 1 ns setup and hold

      So for the patented Rambus, for data rates longer than 1 ns there are
      regions along the bus dependant on data rate and set-up and hold time
      where no valid data can be latched. Assuming 1 ns set-up and hold time
      for the “samplers” as H&F did results in no physical length of bus
      where valid data can be received at data rates of 1ns and greater.

      That’s what Rambus patented, it’s not source synchronus, at high bus
      frequencies it’s just stupid and useless. At very high bus frequencies,
      with data rates near 1ns or faster they had no solution in the first
      place, and what they did practice in every generation of their RDRAM
      products doesn’t match their patent specification in the first place.
      What they patented is what they abandoned long ago in practice, it’s
      what no one infringes on (not even them) and it’s what they continued
      to file with the USPTO to argue for broader and broader claims more
      than fifty times in order to bring their rediculous lawsuits.


      Since the Rambus investors are so vocal about the “rights” that the
      corporation to which they’ve entrusted their enrichment asserts
      allegedly derived from a patent specification that covers apparently
      all combinations of “clock” and “PLL” or “DLL”, perhaps they can
      clarify to us why Horowitz and Farmwald subsequent to their 1990 ‘898
      patent disclosure, in 1992 filed the following specification:

      United States Patent      5,432,823
      Gasbarro ,   et al.     July 11, 1995
      Method and circuitry for minimizing clock-data skew in a bus system


      A bus system is described that minimizes clock-data skew. The bus
      system includes a data bus, a clockline and synchronization circuitry.
      The clockline has two clockline segments. Each clockline segment
      extends the entire length of the data bus and is joined to the other
      clockline segment by a turnaround at one end of the data bus. The
      clockline ensures that clock and data signals travel in the same
      direction. Synchronization circuitry within transmitting devices
      synchronizes data signals to be coupled onto the data bus with the
      clock signal used by other devices to receive the data.

      Inspection of this patent disclosure leads one to think that a source
      synchronous implementation of a looped clock data interface was, in
      1992, rather new to the alleged inventors of the Rambus and its
      implementation was in fact not due exclusively to the “creative genius”
      or “fertile minds” of H&F. In fact it would appear that the primary
      inventor is asserted to be J. Gasbarro; a former graduate student of
      the eminent Dr. Horowitz.

      Perusal of the following paper:
      published more than a year before the ‘898 “kitchen sink” patent
      specification of dram, bus, clock, controller, and whatever; might lead
      one to think that the great leaps that Rambus asserts are only possible
      in light of the ‘898 disclosure were rather not so novel.

      Gasbarro at the time of disclosing his thesis project work in open
      publication (in part funded by John and Jane Q. Taxper through DARPA,
      by the way) on page 332 of the journal publication states, relative to
      providing programmably adjustable clock timing signals for a
      single-chip DRAM based stimulus testing generator:

      “There were two basic approaches to this problem:either build high
      accuracy delay generators using techniques such as PLL delay lines [5],
      or use circuits which are stable and can be easily calibrated, but
      which have low absolute accuracy.”

      In spite of taking the latter approach, reference [5] clearly shows
      that Gasbarro’s understanding of the utility of CMOS based “PLL delay
      lines” (or DLLs) was derived, at least in part from his prior
      conversations while at Xerox with (at least) G. Borrielo concerning
      other Darpa funded developments. None of this information appears to
      have been made available by citation or reference in the prosecutions
      of any Rambus patent or during the assertion of infringement against
      any number of targets by Rambus. This includes the recent infringement
      trial against Hynix during which Dr. Horowitz, under oath,
      disingenuously asserted the importance of the “low skew”
      characteristics of the clock synchronization methods specified in th
      e’898 disclosure as being important to the data transfer speeds
      associated with their “licensed” Rambus products.

      It’s not necessarily surprising that such behavior would be exhibited
      by a person who has made circuitry which in its every essential element
      appears both in the thesis of one of his graduate students and in a
      paper published in April 1989 with that student cited as primary author
      also appear in a 1990 patent disclosure used in the identical fashion
      that that graduate student specified, but claiming entire inventorship
      to Horowitz and Farmwald. We can see this on page 335 of the journal in
      which Gasbarro’s article was published:

      Figure 7, Clocked analog comparitor. is in all of its essential
      elements equivalent to the “input samplers” of the ‘898 disclosure; the
      operration of which was:

      “…simply build two sampling circuits: one which operates on the
      positive transition of the clock, and one which operates on the
      negative transition.”

      It’s also not necessarily surprising in light of the fact that as
      Gasbarro’s synchronization method was being submitted to the USPTO on
      3-06-1992, the first divisional of the ‘898 specification disclosure to
      ripen to an issued patent (5243703 of “JEDEC disclosure” fame) was
      filed the day before, 3-05-1992 with “no new material” that might have
      impact on the patentability of any claims therein; just as a multitude
      of “patent applications” incorporated the useless ‘898 system
      specification to ripen into more than 57 “presumed valid” patents
      incorporating more and more and broader and braoder claims to this very

      Let me make it clear to the fervid investors, I’m very much in favor of
      Rambus getting absolutely everything that’s coming to it. The complaint
      council’s proposed remedy is only a very tiny fraction of that.

    • 37 CFR 1.56 Duty to disclose information material to patent­ability.

      A patent by its very nature is affected with a public interest. The
      public interest is best served, and the most effective patent
      examination occurs when, at the time an application is being examined,
      the Office is aware of and evaluates the teachings of all information
      material to patentability. Each individual associated with the filing
      and prosecution of a patent application has a duty of candor and good
      faith in dealing with the Office, which includes a duty to disclose to
      the Office all information known to that individual to be material to
      patentability as defined in this section. The duty to disclose
      information exists with respect to each pending claim until the claim
      is cancelled or withdrawn from consideration, or the application
      becomes abandoned. Information material to the patentability of a claim
      that is cancelled or withdrawn from consideration need not be submitted
      if the information is not material to the patentability
      of any claim remaining under consideration in the application. There is
      no duty to submit information which is not material to the
      patentability of any existing claim. The duty to disclose all
      information known to be material to patentability is deemed to be
      satisfied if all information known to be material to patentability of
      any claim issued in a patent was cited by the Office or submitted to
      the Office in the manner prescribed by §§ 1.97(b)-(d) and 1.98.
      However, no patent will be granted on an application in connection with
      which fraud on the Office was practiced or attempted or the duty of
      disclosure was violated through bad faith or intentional misconduct.
      The Office encourages applicants to carefully examine:

      (1) Prior art cited in search reports of a foreign patent office in a counterpart application, and

      (2) The closest information over which individuals
      associated with the filing or prosecution of a patent application
      believe any pending claim patentably defines, to make sure that any
      material information contained therein is disclosed to the Office.”

      Rambus has witheld information of its clear knowledge
      affecting the patentability of  a large number of claims
      surrounding their ‘898 written specification of 1990. In particular,
      while claiming to the patent office, the FTC and courts in this country
      and around the world

      Referring to Rambus’ pre-trial brief before the FTC:


      The “Farmwald and Horowitz Inventions”: list is funny enough without the inclusion of :

      “synchronizing the timing of multiple DRAMs by
      generating an internal clock for each DRAM that is set to the midpoint
      between an “early” and “late” clock signal;”

      (Omitting the fact that the ‘898 patent
      specification requires that the bus interface data transmitters be
      operated by this “internal midpoint” clock and its complement; a method
      that is so technically deficient and commercially disadvantageous that
      noone, even Rambus themselves practices it.)

      “performing fine timing adjustments using a delay
      locked loop or DLL (that is, a feedback circuit using delay elements to
      synchronize two signals) on the DRAM.”

      (Omitting the fact that the “delay locked loop” of
      the ‘898 disclosure, besides being non-functional under a broad range
      of conditions, is not only fixed in its output timing characteristics
      and therefore incapable of any “fine timing adjustments”, ti serves
      only to generate the unused “internal midpoint” clock referred to

      Rambus had material information relevant to the
      patentability of claims associated with this aspect and many others in
      their specification of alleged invention. They’ve certainly done their
      best to conceal that information and misrepresent the utility and value
      of these “fundamental technologies” as well as the original inventors
      of the methods, practices and devices. Sure-shred isn’t able to get to
      some materials, though.

      So come on bigmouthed Rambus investors, in clear and
      detailed fashion tell me how I’m wrong. Tell me that the clock at the
      midpoint of early and late clocks is really what operates the input
      samplers and output transmitters of any generation of RDRAM “slave”
      module product. Tell me it isn’t RCLK derived from 
      “CLockToMaster” and TCLK derived at a phase shift of 90 degrees from
      “ClockFromMaster” as stated in the “A 500-Megabyts/s Data-Rate 4.5M
      DRAM” (IEEE J. SOL-ST Cir. Vol 28, No.4 Apr 1993, pp 490-498).

      Tell me how the following statement from US patent
      5432823 can’t possibly refer to the then “prior art” of the Horowitz
      and Farmwald “Rambus” specification (and the quotes are there for a

      “For certain prior art synchronous bus systems with sufficiently short
      bus and clockline lengths, clock-data skew might not be a concern
      because clock and data signals have only a short distance to travel and
      arrive nearly instantaneously. Within
      a synchronous bus system with a long data bus and a long clockline,
      clock-data skew is often a concern, however, especially if high clock
      speeds are desired. Within many prior art synchronous bus systems, a
      clock period must exceed clock signal
      propagation delay. Put another way, clock speed must generally slow as
      clockline length increases. This prior art relationship is expressed by
      Expression 1:

      “(1) Clock Period>set-up time of data to clock signal+hold time of data to clock signal+clock-data skew”

      And since the method of reduction of clock-data skew
      is largely that practiced in the commercial Rambus, why is the H&F
      ‘898 specification not referenced? Conversely, if the ‘898
      specification is the means by which a Rambus is constructed and
      synchronized to an external clock, why is the information in th
      Gasbarro et. al. patent never referred to?


  2. Our legal system has decided on several occasions who holds the moral high ground in this epic battle. It’s nice to know Gesmer Updegrove see’s so clearly through those pesky judgements, still standing strongly in support of poor JEDEC. I imagine slaving free of compensation on behalf of Micron et all fills the time awaiting OJ Simpson’s need to once again show the system the error of its ways.

  3. You sir, are a saint. Fighting the good fight for only pure satisfaction.  I shall keep you in my prayers.

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